Worldwide leaders in hardware/software co-verification and Network-on-Chip (NoC) interconnect IP combine forces to reduce System-on-Chip (SoC) design time and effort.
Arteris Inc., the leading supplier of network-on-chip (NoC) interconnect IP solutions and EVE, the leader in hardware/software co-verification, today announced an integrated solution enabling SoC developers to easily generate and use actual SoC RTL implementations on EVE Zebu server emulation hardware. This integration allows SoC developers to create and ship their products sooner.
Arteris and EVE have worked together to integrate NoC interconnect creation and deployment with hardware emulation. The design flow allows the interconnect IP for the complete SoC to be assembled in Arteris FlexNoC, where the RTL is generated for input into the EVE Zebu emulation platform. This flow greatly simplifies architectural exploration and testing, allowing multiple test iterations in a single day using the actual applications that will be run on the final SoC.
This integration work was funded by the European Community in the framework of the FEDER project, where ENSTA ParisTech is also a key partner.
“The Arteris-EVE integration allows us to easily test the impact of different cache sizes and the number of computing cores on metrics like latency and bandwidth,” said Dr. Woo-hyun Paik, Vice President and Research Fellow of the DIS Group, LG Electronics.
“We are able to quickly iterate tests on EVE Zebu while using the exact same NoC interconnect we will use on the finished silicon SoC.”
Dr. Luc Burgun, EVE’s chief executive officer and president said, “This integration will benefit all our common customers, especially for mobile and wireless SoCs where Arteris FlexNoC is the best sustainable interconnect solution for connecting IPs and where we expect to see lots of changes in terms of design architecture.”
“The Arteris-EVE partnership has opened new directions for architectural analysis because only fast emulation provides the horsepower required to accurately validate multiple design architectures per day,” said K. Charles Janac, President and CEO of Arteris. “This approach perfectly fits our strategy to enable our SoC customers to make the most efficient use of silicon area and power as well as optimize software performance based on actual data traffic information.”
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.
Founded by networking experts and offering the first commercially available Network-on- Chip IP products, Arteris operates globally with headquarters in San Jose, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech.
More information can be found at www.arteris.com.
EVE is the worldwide leader in hardware/software co-verification solutions, offering fast transaction-based co-emulation and in-circuit emulation, with installations at nine of the top 10 semiconductor companies. EVE products shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products can be integrated with transaction-level ESL tools and software debuggers, target hardware systems, as well as Verilog, SystemVerilog and VHDL simulators. EVE is a member of ARM, Mentor Graphics, Real Intent, Springsoft and Synopsys Partner programs.